EN87C196LB20

Product Summary

The EN87C196LB20 is a high-performance 16-bit microcontroller with integrated support for the J1850 communication protocol. The EN87C196LB20 is composed of a high-speed core with the following peripherals: an asynchronous/synchronous serial I/O port (8096 compatible) with a dedicated 16-bit baud-rate generator; an additional synchronous serial I/O port with full duplex master/slave transceivers; a six-channel A/D converter with sample and hold; a flexible timer/counter structure with prescaler, cascading, and quadrature capabilities; six modularized, multiplexed high-speed I/O for capture and compare (called event processor array) with 200 ns resolution and double buffered inputs; and a sophisticated prioritized interrupt structure with programmable peripheral transaction server (PTS). The clock doubler circuitry and oscillator output signal enable a 4 MHz resonator to achieve the same internal clock speed as a more costly 8 MHz resonator in previous applications. This same circuitry can drive other devices where a separate resonator was required in the past. Another costsavings feature of the EN87C196LB20 is the fact that the I/O ports are driven low at reset, avoiding the need for pull-up resistors.

Parametrics

EN87C196LB20 absolute maximum ratings: (1)Storage Temperature: -60℃ to +150℃; (2)Voltage from VPP or EA# to VSS or ANGND: -0.5V to +13.0 V; (3)Voltage from any other pin to VSS or ANGND: -0.5V to +7.0V; (4)Power Dissipation: 0.5W; (5)TA (Ambient Temperature Under Bias: -40℃ to +125℃; (6)VCC (Digital Supply Voltage): 4.50V to 5.50V; (7)VREF (Analog Supply Voltage): 4.50V to 5.50V; (8)FXTAL1 (Input Frequency): PLL in 2x mode: 4 MHz to 10 MHz, PLL in 1x mode: 8 MHz to 20 MHz.

Features

EN87C196LB20 features: (1)20 MHz operatio; (2)24 Kbytes of on-chip OTPROM; (3)768 bytes of on-chip register RAM; (4)Register-to-register architecture; (5)Peripheral transaction server (PTS) with high-speed, microcoded interrupt service routines; (6)Integrated, industry-standard J1850 communication protocol; (7)Six-channel/10-bit A/D with sample and hold; (8)High-speed event processor array; (9)Six capture/compare channels; (10)Two compare-only channels; (11)Two 16-bit software timers; (12)Full-duplex serial I/O port with dedicated baud-rate generator; (13)Enhanced full-duplex, synchronous serial I/O port (SSIO); (14)Programmable 8- or 16-bit external bus; (15)Optional clock doubler with programmable clock output signal; (16)SFR register that indicates the source of the last reset; (17)Design enhancements for EMI reduction; (18)Oscillator failure detection circuitry; (19)Watchdog timer (WDT); (20)–40℃ to +125℃ ambient temperature; (21)52-pin PLCC package.

Diagrams