MC68HC908QY4CPE

Product Summary

The MC68HC908QY4CPE is a low-cost, high-performance 8-bit microcontroller unit (MCU). The MC68HC908QY4CPE is a Complex Instruction Set Computer (CISC) with Von Neumann architecture. The MC68HC908QY4CPE uses the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types.

Parametrics

MC68HC908QY4CPE absolute maximum ratings: (1)Supply voltage VDD:–0.3V to +6.0V; (2)Input voltage VIN VSS :–0.3V to VDD +0.3V; (3)Mode entry voltage, IRQ pin VTST VSS:–0.3V to +9.1V; (4)Maximum current per pin excluding PTA0–PTA5, VDD, and VSS; (5)I: ±15mA; (6)Maximum current for pinsPTA0–PTA5 IPTA0—IPTA5: ±25mA; (7)Storage temperature TSTG:–55℃ to +150℃; (8)Maximum current out of VSS IMVSS: 100mA; (9) Maximum current into VDD IMVDD: 100mA.

Features

MC68HC908QY4CPE features: (1)High-performance M68HC08 CPU core; (2)Fully upward-compatible object code with M68HC05 Family; (3)5-V and 3-V operating voltages (VDD); (4)8-MHz internal bus operation at 5 V, 4-MHz at 3 V; (5)Trimmable internal oscillator: 3.2 MHz internal bus operation, 8-bit trim capability, ±25% untrimmed, ±5% trimmed; (6)Auto wake-up from STOP capability; (7)Configuration (CONFIG) register for MCU configuration options, including: Low-voltage inhibit (LVI) trip point; (8)In-system FLASH programming; (9)FLASH security; (10)On-chip in-application programmable FLASH memory (with internal program/erase voltage generation): 4096 bytes; (11)128 bytes of on-chip random-access memory (RAM); (12)2-channel, 16-bit timer interface module (TIM); (13)4-channel, 8-bit analog-to-digital converter (ADC) on MC68HC908QY2, MC68HC908QY4, MC68HC908QT2, and MC68HC908QT4; (14)5 or 13 bidirectional input/output (I/O) lines and one input only; (15)6-bit keyboard interrupt with wakeup feature (KBI); (16)Low-voltage inhibit (LVI) module features: Software selectable trip point in CONFIG register; (17)Computer operating properly (COP) watchdog; (18)Low-voltage detection with reset; (19)Illegal opcode detection with reset; (20)Illegal address detection with reset.

Diagrams